ES

Eiji Sugiyama

SL Semiconductor Energy Laboratory: 37 patents #252 of 1,113Top 25%
Fujitsu Limited: 8 patents #3,989 of 24,456Top 20%
EC Elmo Co.: 8 patents #7 of 62Top 15%
Honda Motor Co.: 5 patents #4,418 of 21,052Top 25%
TO Toyota: 4 patents #6,703 of 26,838Top 25%
HI Hitachi: 3 patents #10,712 of 28,497Top 40%
TC Taiho Kogyo Co.: 2 patents #102 of 332Top 35%
KC Koyo Seiko Co.: 1 patents #363 of 749Top 50%
TI Toray Industries: 1 patents #2,000 of 3,690Top 55%
Overall (All Time): #34,896 of 4,157,543Top 1%
64
Patents All Time

Issued Patents All Time

Showing 51–64 of 64 patents

Patent #TitleCo-InventorsDate
7354801 Method for manufacturing semiconductor device Kyosuke Ito 2008-04-08
D565621 TV camera Akira Yamane, Tetsuro Kato 2008-04-01
7335951 Semiconductor device and method for manufacturing the same Kazuo Nishi, Hiroki Adachi, Junya Maruyama, Naoto Kusumoto, Yuusuke Sugawara +2 more 2008-02-26
D543224 Surveillance television camera Tetsuro Kato 2007-05-22
5570766 End bearing for one-way clutch Eichi Sato, Yoshihiro Kaku, Yuji Yokota, Hiroshi Shibata, Masanori Hatanaka +2 more 1996-11-05
5508634 Semiconductor integrated circuit device of dual configuration having enhanced soft error withstanding capacity 1996-04-16
5436572 Semiconductor integrated circuuit device of dual configuration having enhanced soft error withstanding capacity 1995-07-25
5242741 Boronized sliding material and method for producing the same Motoshi Hayashi 1993-09-07
4952997 Semiconductor integrated-circuit apparatus with internal and external bonding pads Mitsuaki Natsume, Toshiharu Saito 1990-08-28
4904887 Semiconductor integrated circuit apparatus Mitsuaki Natsume, Toshiharu Saito 1990-02-27
4891729 Semiconductor integrated-circuit apparatus Mitsuaki Natsume, Toshiharu Saito 1990-01-02
4779009 Master-slave type flip-flop circuit Hiroyuki Tsunoi, Motohiro Seto 1988-10-18
4779011 Latch circuit having two hold loops Hiroyuki Tsunoi, Yasunori Kanai, Motohiro Seto, Naoyuki Ando 1988-10-18
4599521 Bias circuit with voltage and temperature compensation for an emitter coupled logic circuit Yasunori Kanai, Kazumasa Nawata 1986-07-08