Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5216296 | Logic circuit having sharper falling edge transition | Hiroyuki Tsunoi, Toshiaki Sakai, Hiroki Yada, Hisayosi Ooba, Takayuki Tsuru +2 more | 1993-06-01 |
| 5144158 | ECL latch circuit having a noise resistance circuit in only one feedback path | Yasunori Kanai, Mitsuhisa Shimizu, Hiroki Yada, Taichi Saitoh, Toshiaki Sakai | 1992-09-01 |
| 4918563 | ECL gate array semiconductor device with protective elements | Yasunori Kanai, Mitsuhisa Shimizu, Toshiaki Sakai | 1990-04-17 |
| 4866303 | ECL gate array with collector resistance compensation for distance from power supply pad | Yasunori Kanai, Mitsuhisa Shimizu | 1989-09-12 |
| 4678935 | Inner bias circuit for generating ECL bias voltages from a single common bias voltage reference | Yasunori Kanai | 1987-07-07 |
| 4599521 | Bias circuit with voltage and temperature compensation for an emitter coupled logic circuit | Yasunori Kanai, Eiji Sugiyama | 1986-07-08 |
| 4375999 | Method of manufacturing a semiconductor device | Hirokazu Suzuki | 1983-03-08 |
| 4278897 | Large scale semiconductor integrated circuit device | Kenichi Ohno, Tohru Hosomizu | 1981-07-14 |