Kinhing P. Tsang has been granted 28 US patents while listed as an inventor at Seagate Technology . The first was granted in 1992 and the most recent in December 2025. Kinhing P. Tsang ranks #134,628 of 4,157,543 US inventors in our database (top 3.2%). Patent records list Kinhing P. Tsang in Plymouth, MN, US.
Patents per Year Patents granted per year, 1992 to 2013 Bar chart with a peak of 4 patents in 2006. peak 4 1992: 1 patents 1992 1993: 1 patents 1995: 1 patents 1995 1996: 1 patents 1998: 2 patents 1998 2000: 3 patents 2001: 2 patents 2001 2002: 3 patents 2005: 3 patents 2005 2006: 4 patents 2007: 1 patents 2007 2008: 1 patents 2010: 2 patents 2010 2011: 1 patents 2013: 1 patents 2013 Issued Patents All Time
Showing 1–25 of 28 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
12497001 Information processing apparatus, program, computer readable recording medium, and information processing method Miyuki Hanaoka , Keisuke Unno , Jun Murata 2025-12-16
8352826 System for providing running digital sum control in a precoded bit stream Cenk Argon 2013-01-08
$24,082,000
8037398 System for precoding parity bits to meet predetermined modulation constraints Cenk Argon , Alexander Kuznetsov 2011-10-11
$7,258,000
7741980 Providing running digital sum control in a precoded bit stream using precoder aware encoding Cenk Argon 2010-06-22
$9,290,000
7683810 Code design with decreased transition density and reduced running digital sum — 2010-03-23
$16,153,000
7340665 Shared redundancy in error correcting code — 2008-03-04
$42,820,000
7218256 DC-free code having limited error propagation and limited complexity Chandra C. Varanasi 2007-05-15
$11,062,000
7088268 DC free code design with state dependent mapping — 2006-08-08
$19,058,000
7084789 DC-free code having limited error propagation and limited complexity Chandra C. Varanasi 2006-08-01
$83,385,000
7002492 High rate running digital sum-restricted code Michael J. Link 2006-02-21
$11,510,000
6989776 Generation of interleaved parity code words having limited running digital sum values — 2006-01-24
$12,121,000
6961010 DC-free code design with increased distance between code words — 2005-11-01
$7,490,000
6867713 DC free code design with state dependent mapping — 2005-03-15
$10,397,000
6839004 High rate run length limited code — 2005-01-04
$12,041,000
6480125 Method and apparatus for efficient encoding of large data words at high code rates Bernardo Rub 2002-11-12
6467060 Mass storage error correction and detection system, method and article of manufacture Krishna R. Malakapalli 2002-10-15
6393598 Branch metric compensation for digital sequence detection Robert E. Kost , Kenneth R. Burns 2002-05-21
6288655 Encoding and decoding techniques for data in 24 bit sequence Bernardo Rub 2001-09-11
6198582 Efficient run length limited code with short interleaved constraint Bernardo Rub 2001-03-06
6111834 Data storage system having efficient block code implementation Bernardo Rub 2000-08-29
$63,638,000
6052072 System and scheme for maximum transition run length codes with location dependent constraints Bernardo Rub 2000-04-18
$19,309,000
6011497 Location dependent maximum transition run length code with alternating code word length and efficient K constraint Bernardo Rub 2000-01-04
$19,300,000
5781133 Method and apparatus for implementing run length limited codes — 1998-07-14
$20,193,000
5731768 Method and apparatus for implementing codes with maximum transition run length — 1998-03-24
$13,249,000
5537112 Method and apparatus for implementing run length limited codes in partial response channels — 1996-07-16
$22,634,000