Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10325058 | Method for verifying a layout designed for a semiconductor integrated circuit and a computer system for performing the same | JAEICK SON, Sunghoon Kim | 2019-06-18 |
| 8878253 | Semiconductor devices | Hong-Soo Kim, Hwa-Kyung Shin, Jong Ho Lim | 2014-11-04 |