Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11861280 | Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system | In Huh, Jeong-Hoon Ko, Hyo-jin Choi, Seung-ju Kim, Chang Wook Jeong +6 more | 2024-01-02 |
| 11281832 | Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system | In Huh, Jeong-Hoon Ko, Hyo-jin Choi, Seung-ju Kim, Chang Wook Jeong +6 more | 2022-03-22 |
| 6914850 | Address buffer having (N/2) stages | — | 2005-07-05 |
| 6046947 | Integrated circuit memory devices having direct access mode test capability and methods of testing same | Kye-hyun Kyung | 2000-04-04 |