JO

Jong-Hoon Oh

Samsung: 40 patents #2,691 of 75,807Top 4%
Infineon Technologies Ag: 23 patents #386 of 7,486Top 6%
HE Hynix (Hyundai Electronics): 18 patents #14 of 1,604Top 1%
QA Qimonda Ag: 15 patents #32 of 575Top 6%
SH Sk Hynix: 7 patents #1,069 of 4,849Top 25%
GT G-Link Technology: 7 patents #1 of 3Top 35%
PT Pulsus Technologies: 5 patents #1 of 11Top 10%
HA Hyundai Electronics America: 3 patents #30 of 148Top 25%
AC Ajou University Industry-Academic Cooperation: 2 patents #99 of 591Top 20%
📍 Seongnam-si, CA: #11 of 102 inventorsTop 15%
Overall (All Time): #9,806 of 4,157,543Top 1%
121
Patents All Time

Issued Patents All Time

Showing 76–100 of 121 patents

Patent #TitleCo-InventorsDate
D546305 Portable phone Jin-Soo Kim, Nam-Mi Kim, Chang-Hwan Hwang 2007-07-10
7224626 Redundancy circuits for semiconductor memory 2007-05-29
7177216 Twin-cell bit line sensing configuration Jungwon Suh 2007-02-13
D536324 Portable phone Jin-Soo Kim, Nam-Mi Kim, Chang-Hwan Hwang 2007-02-06
D536323 Portable phone Jin-Soo Kim, Nam-Mi Kim, Chang-Hwan Hwang 2007-02-06
7124052 Multichip package with clock frequency adjustment 2006-10-17
7095669 Refresh for dynamic cells with weak retention 2006-08-22
D521482 Cellular phone Jin-Soo Kim, Nam-Mi Kim, Chang-Hwan Hwang 2006-05-23
D521484 Cellular phone Jin-Soo Kim, Nam-Mi Kim, Chang-Hwan Hwang 2006-05-23
7042777 Memory device with non-variable write latency 2006-05-09
7042786 Memory with adjustable access time 2006-05-09
7027344 High-speed semiconductor memory having internal refresh control 2006-04-11
D518466 Cellular phone Nam-Mi Kim, Chang-Hwan Hwang, Jin-Soo Kim 2006-04-04
6996016 Echo clock on memory system having wait information 2006-02-07
6985398 Memory device having multiple array structure for increased bandwidth 2006-01-10
6982911 Memory device with common row interface 2006-01-03
6909660 Random access memory having driver for reduced leakage current 2005-06-21
6765976 Delay-locked loop for differential clock signals 2004-07-20
6606272 Method and circuit for processing output data in pipelined circuits Young Seog Kim 2003-08-12
6529428 Multi-bit parallel testing for memory devices 2003-03-04
6501670 High speed memory architecture and busing 2002-12-31
6496032 Method and structure for efficiently placing and interconnecting circuit blocks in an integrated circuit 2002-12-17
6445641 Memory device with time shared data lines 2002-09-03
6275441 Data input/output system for multiple data rate memory devices 2001-08-14
6108248 Column address strobe signal generator for synchronous dynamic random access memory 2000-08-22