Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9716129 | Memory device and electronic apparatus including the same | Kyu-Rie Sim, Dae-Hwan Kang | 2017-07-25 |
| 9691459 | Semiconductor memory device including shorted variable resistor element of memory cell | Bo-Young Seo, Suk-Soo Pyo, Yong-Kyu Lee, Dae-Shik Kim | 2017-06-27 |
| 8451656 | Multi-level memory devices and methods of operating the same | Dae Won Ha | 2013-05-28 |
| 8213223 | Multi-level memory devices and methods of operating the same | Dae Won Ha | 2012-07-03 |
| 8036018 | Non-volatile memory devices including stacked NAND-type resistive memory cell strings | Dae Won Ha | 2011-10-11 |
| 8026543 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same | Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Choong-Man Lee +10 more | 2011-09-27 |
| 7843718 | Non-volatile memory devices including stacked NAND-type resistive memory cell strings and methods of fabricating the same | Dae Won Ha | 2010-11-30 |
| 7482616 | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same | Yoon-Jong Song, Young-Nam Hwang, Sang-Don Nam, Sung-Lae Cho, Choong-Man Lee +10 more | 2009-01-27 |
| 7465675 | Method of forming a phase change memory device having a small area of contact | — | 2008-12-16 |
| 7411208 | Phase-change memory device having a barrier layer and manufacturing method | Young-Nam Hwang, Su-Jin Ahn, Sung-Lae Cho, Se-Ho Lee, Kyung-Chang Ryoo +3 more | 2008-08-12 |
| 7112492 | Methods of fabricating semiconductor devices with scalable two transistor memory cells | Su-Jin Ahn, Hyoung Joon Kim | 2006-09-26 |
| 6903409 | Semiconductor devices with scalable two transistor memory cells | Su-Jin Ahn, Hyoung Joon Kim | 2005-06-07 |
| 6870268 | Integrated circuit devices formed through selective etching of an insulation layer to increase the self-aligned contact area adjacent a semiconductor region | Jae-Goo Lee | 2005-03-22 |
| 6753227 | Method of fabricating MOS transistors | Chang-Hyun Cho, Ki-Nam Kim | 2004-06-22 |
| 6649490 | METHODS FOR FORMING INTEGRATED CIRCUIT DEVICES THROUGH SELECTIVE ETCHING OF AN INSULATION LAYER TO INCREASE THE SELF-ALIGNED CONTACT AREA ADJACENT A SEMICONDUCTOR REGION AND INTEGRATED CIRCUIT DEVICES FORMED THEREBY | Jae-Goo Lee | 2003-11-18 |
| 6458680 | Method of fabricating contact pads of a semiconductor device | Tae-Young Chung, Jae-Goo Lee | 2002-10-01 |
| 6355547 | Method of forming a self-aligned contact pad for a semiconductor device | Jae-Goo Lee, Chang-Hyun Cho | 2002-03-12 |
| 6337282 | Method for forming a dielectric layer | Ju-Wan Kim, Byung Keun Hwang, Sung Jin Kim, Jue-Goo Lee, Chang-Hyun Cho | 2002-01-08 |
| 6335233 | Method for fabricating MOS transistor | Chang-Hyun Cho, Mi-Hyang Lee, Dae Won Ha | 2002-01-01 |