Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12217811 | Programmable logic device with design for test functionality | Chihhung Liao, Shieh Huan Yen | 2025-02-04 |
| 12149244 | Configuration latch for programmable logic device | Chihhung Liao | 2024-11-19 |
| 11935618 | Area-efficient configuration latch for programmable logic device | Chihhung Liao, Shieh Huan Yen | 2024-03-19 |
| 11848066 | Programmable logic device with design for test functionality | Chihhung Liao, Shieh Huan Yen | 2023-12-19 |
| 11848671 | Configuration latch for programmable logic device | Chihhung Liao | 2023-12-19 |
| 11652486 | Sectional configuration for programmable logic devices | Chihhung Liao | 2023-05-16 |
| 10148270 | Switchable power islands having configurably on routing paths | Pinaki Chakrabarti, Wilma Waiman Shiao, Vishnu A. Patil, Lalit Narain Sharma | 2018-12-04 |
| 8487652 | Adjustable interface buffer circuit between a programmable logic device and a dedicated device | Senani Gunaratna, Wilma Waiman Shiao | 2013-07-16 |
| 8091001 | FPGA programming structure for ATPG test coverage | Stephen U. Yao, Darwin D. Q. Samson | 2012-01-03 |
| 8018248 | Adjustable interface buffer circuit between a programmable logic device and a dedicated device | Senani Gunaratna, Wilma Waiman Shiao | 2011-09-13 |
| 7646216 | Low power mode | Wilma Waiman Shiao, Stephen U. Yao | 2010-01-12 |
| 6552410 | Programmable antifuse interfacing a programmable logic and a dedicated device | David D. Eaton, Kevin K. Yee, E. Thomas Hart, Andrew K. Chan, Neal PALMER +3 more | 2003-04-22 |
| 6542096 | Serializer/deserializer embedded in a programmable device | Andrew K. Chan, James M. Apland, Senani Gunaratna, SunilKumar G. Mudunuri | 2003-04-01 |
| 6097651 | Precharge circuitry in RAM circuit | Andrew K. Chan, James M. Apland | 2000-08-01 |