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Programmable logic device with design for test functionality |
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Configuration latch for programmable logic device |
Chihhung Liao |
2024-11-19 |
| 11935618 |
Area-efficient configuration latch for programmable logic device |
Chihhung Liao, Shieh Huan Yen |
2024-03-19 |
| 11848066 |
Programmable logic device with design for test functionality |
Chihhung Liao, Shieh Huan Yen |
2023-12-19 |
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Configuration latch for programmable logic device |
Chihhung Liao |
2023-12-19 |
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Sectional configuration for programmable logic devices |
Chihhung Liao |
2023-05-16 |
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Switchable power islands having configurably on routing paths |
Pinaki Chakrabarti, Wilma Waiman Shiao, Vishnu A. Patil, Lalit Narain Sharma |
2018-12-04 |
| 8487652 |
Adjustable interface buffer circuit between a programmable logic device and a dedicated device |
Senani Gunaratna, Wilma Waiman Shiao |
2013-07-16 |
| 8091001 |
FPGA programming structure for ATPG test coverage |
Stephen U. Yao, Darwin D. Q. Samson |
2012-01-03 |
| 8018248 |
Adjustable interface buffer circuit between a programmable logic device and a dedicated device |
Senani Gunaratna, Wilma Waiman Shiao |
2011-09-13 |
| 7646216 |
Low power mode |
Wilma Waiman Shiao, Stephen U. Yao |
2010-01-12 |
| 6552410 |
Programmable antifuse interfacing a programmable logic and a dedicated device |
David D. Eaton, Kevin K. Yee, E. Thomas Hart, Andrew K. Chan, Neal PALMER +3 more |
2003-04-22 |
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Andrew K. Chan, James M. Apland, Senani Gunaratna, SunilKumar G. Mudunuri |
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Precharge circuitry in RAM circuit |
Andrew K. Chan, James M. Apland |
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