Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9690725 | Camera control interface extension with in-band interrupt | — | 2017-06-27 |
| 9684624 | Receive clock calibration for a serial bus | — | 2017-06-20 |
| 9681049 | System and methods for damping lens ringing | — | 2017-06-13 |
| 9678828 | Error detection capability over CCIe protocol | — | 2017-06-13 |
| 9673969 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state | George Alan Wiley, Chulkyu Lee, Joseph Cheung | 2017-06-06 |
| 9673968 | Multi-wire open-drain link with data symbol transition based clocking | Joseph Cheung, George Alan Wiley | 2017-06-06 |
| 9673961 | Multi-lane N-factorial (N!) and other multi-wire communication systems | — | 2017-06-06 |
| 9672176 | Slave identifier scanning and hot-plug capability over CCIe bus | — | 2017-06-06 |
| 9639499 | Camera control interface extension bus | George Alan Wiley, Joseph Cheung | 2017-05-02 |
| 9621332 | Clock and data recovery for pulse based multi-wire link | — | 2017-04-11 |
| 9582457 | Camera control interface extension bus | George Alan Wiley, Joseph Cheung | 2017-02-28 |
| 9552325 | Camera control interface extension bus | George Alan Wiley, Joseph Cheung | 2017-01-24 |
| 9519603 | Method and apparatus to enable multiple masters to operate in a single master bus architecture | Richard Dominic Wietfeldt, George Alan Wiley | 2016-12-13 |
| 9490964 | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period | — | 2016-11-08 |
| 9444612 | Multi-wire single-ended push-pull link with data symbol transition based clocking | George Alan Wiley, Joseph Cheung | 2016-09-13 |
| 9426082 | Low-voltage differential signaling or 2-wire differential link with symbol transition clocking | — | 2016-08-23 |
| 9374216 | Multi-wire open-drain link with data symbol transition based clocking | Joseph Cheung, George Alan Wiley | 2016-06-21 |
| 9363071 | Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches | Chulkyu Lee, George Alan Wiley, Joseph Cheung | 2016-06-07 |
| 9337997 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state | George Alan Wiley, Chulkyu Lee, Joseph Cheung | 2016-05-10 |
| 9319178 | Method for using error correction codes with N factorial or CCI extension | — | 2016-04-19 |
| 9313058 | Compact and fast N-factorial single data rate clock and data recovery circuits | George Alan Wiley, Chulkyu Lee | 2016-04-12 |
| 9203599 | Multi-lane N-factorial (N!) and other multi-wire communication systems | — | 2015-12-01 |
| 9178690 | N factorial dual data rate clock and data recovery | — | 2015-11-03 |
| 9172426 | Voltage mode driver circuit for N-phase systems | Chulkyu Lee, George Alan Wiley | 2015-10-27 |
| 9118457 | Multi-wire single-ended push-pull link with data symbol transition based clocking | George Alan Wiley, Joseph Cheung | 2015-08-25 |