Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10545886 | Clock line driving for single-cycle data over clock signaling and pre-emption request in a multi-drop bus | Lalan Jee Mishra | 2020-01-28 |
| 10528503 | Real-time dynamic addressing scheme for device priority management | Lalan Jee Mishra | 2020-01-07 |
| 10521392 | Slave master-write/read datagram payload extension | Lalan Jee Mishra, Mohit Kishore Prasad, Christopher Kong Yee Chun | 2019-12-31 |
| 10515044 | Communicating heterogeneous virtual general-purpose input/output messages over an I3C bus | Radu Pitigoi-Aron, Lalan Jee Mishra | 2019-12-24 |
| 10496568 | Technique for RFFE and SPMI register-0 write datagram functional extension | Lalan Jee Mishra, Helena Deirdre O'Shea, ZhenQi CHEN | 2019-12-03 |
| 10482057 | Multi-protocol dynamic address allocation | Radu Pitigoi-Aron, Douglas Wayne Hoffman | 2019-11-19 |
| 10482055 | Hardware event priority sensitive programmable transmit wait-window for virtual GPIO finite state machine | Lalan Jee Mishra, Mohit Kishore Prasad | 2019-11-19 |
| 10474622 | Method and apparatus for latency management of data communication over serial bus | Lalan Jee Mishra | 2019-11-12 |
| 10467154 | Multi-port multi-sideband-GPIO consolidation technique over a multi-drop serial bus | Lalan Jee Mishra, Christopher Kong Yee Chun, Mohit Kishore Prasad, Chris Rosolowski | 2019-11-05 |
| 10452603 | Sensors global bus | Radu Pitigoi-Aron, Douglas Wayne Hoffman | 2019-10-22 |
| 10447464 | Super-speed UART with pre-frame bit-rate and independent variable upstream and downstream rates | Lalan Jee Mishra, Elisha Ulmer | 2019-10-15 |
| 10445270 | Configuring optimal bus turnaround cycles for master-driven serial buses | Elisha Ulmer, Lalan Jee Mishra | 2019-10-15 |
| 10423551 | Ultra-short RFFE datagrams for latency sensitive radio frequency front-end | Lalan Jee Mishra, Helena Deirdre O'Shea | 2019-09-24 |
| 10417172 | Sensors global bus | Radu Pitigoi-Aron, Douglas Wayne Hoffman | 2019-09-17 |
| 10417161 | Efficient technique for communicating between devices over a multi-drop bus | Helena Deirdre O'Shea, Lalan Jee Mishra, Amit Gil, Gary Chang, Mohit Kishore Prasad +1 more | 2019-09-17 |
| 10402365 | Data lane validation procedure for multilane protocols | Radu Pitigoi-Aron, Lalan Jee Mishra | 2019-09-03 |
| 10353837 | Method and apparatus to enable multiple masters to operate in a single master bus architecture | Shoichiro Sengoku, George Alan Wiley | 2019-07-16 |
| 10310585 | Replacement physical layer (PHY) for low-speed peripheral component interconnect (PCI) express (PCIe) systems | Shaul Yohai Yifrach, Amit Gil, James Lionel Panian, Ofer Rosenberg | 2019-06-04 |
| 10303643 | Enhanced virtual GPIO with multi-mode modulation | Lalan Jee Mishra, Mohit Kishore Prasad, James Lionel Panian | 2019-05-28 |
| 10289579 | Digital aggregation of interrupts from peripheral devices | Lalan Jee Mishra, Peter Jivan Shah | 2019-05-14 |
| 10289582 | Enhanced serial peripheral interface | Lalan Jee Mishra | 2019-05-14 |
| 10241953 | Dynamic data-link selection over common physical interface | Lalan Jee Mishra, James Lionel Panian | 2019-03-26 |
| 10241955 | Dynamically adjustable multi-line bus shared by multi-protocol devices | Radu Pitigoi-Aron | 2019-03-26 |
| 10146727 | Enhanced virtual GPIO with multi-mode modulation | Lalan Jee Mishra, Mohit Kishore Prasad, James Lionel Panian | 2018-12-04 |
| 10140242 | General purpose input/output (GPIO) signal bridging with I3C bus interfaces and virtualization in a multi-node network | Lalan Jee Mishra, Radu Pitigoi-Aron | 2018-11-27 |