Issued Patents All Time
Showing 26–30 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8848429 | Latch-based array with robust design-for-test (DFT) features | Ramaprasath Vilangudipitchai, Gaurav Bhargava | 2014-09-30 |
| 6763367 | Pre-reduction technique within a multiplier/accumulator architecture | Kevin John Nowka | 2004-07-13 |
| 6584485 | 4 to 2 adder | Naoaki Aoki, Sang Hoo Dhong, Nobuo Kojima | 2003-06-24 |
| 6578063 | 5-to-2 binary adder | Nobuo Kojima, Kevin John Nowka | 2003-06-10 |
| 6335900 | Method and apparatus for selectable wordline boosting in a memory device | Hung C. Ngo, Kevin John Nowka | 2002-01-01 |