Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405792 | Processing unit including a dynamically allocatable vector register file for non-vector instruction processing | Darshan Kumar Nandanwar, Sagar Bamashetti | 2025-09-02 |
| 12299301 | Methods and systems for altering the path of data movement for large-sized memory transactions | Darshan Kumar Nandanwar, Sharath Kumar NAGILLA | 2025-05-13 |
| 12282447 | Execution unit sharing between processing cores in a cluster of a system-on-chip (SoC) | Sharath Kumar NAGILLA, Darshan Kumar Nandanwar | 2025-04-22 |
| 11940914 | Performance aware partial cache collapse | Sharath Kumar NAGILLA, Darshan Kumar Nandanwar, Nirav Narendra Desai, Venkata Biswanath Devarasetty | 2024-03-26 |
| 11836086 | Access optimized partial cache collapse | Sharath Kumar NAGILLA, Darshan Kumar Nandanwar, Nirav Narendra Desai, Venkata Biswanath Devarasetty | 2023-12-05 |