Issued Patents All Time
Showing 26–50 of 122 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812057 | Termination circuit to reduce attenuation of signal between signal producing circuit and display device | — | 2017-11-07 |
| 9811499 | Transcoding and transmission over a serial bus | Shoichiro Sengoku, Joseph Cheung | 2017-11-07 |
| 9711041 | N-phase polarity data transfer | Glenn D. Raskin | 2017-07-18 |
| 9684487 | Line-multiplexed UART | Lalan Jee Mishra, Richard Dominic Wietfeldt | 2017-06-20 |
| 9680666 | N-phase phase and polarity encoded serial interface | Glenn D. Raskin, Chulkyu Lee | 2017-06-13 |
| 9673969 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state | Shoichiro Sengoku, Chulkyu Lee, Joseph Cheung | 2017-06-06 |
| 9673968 | Multi-wire open-drain link with data symbol transition based clocking | Shoichiro Sengoku, Joseph Cheung | 2017-06-06 |
| 9639499 | Camera control interface extension bus | Shoichiro Sengoku, Joseph Cheung | 2017-05-02 |
| 9621333 | Adaptation to 3-phase signal swap within a trio | Ohjoon Kwon | 2017-04-11 |
| 9584227 | Low-power mode signal bridge for optical media | — | 2017-02-28 |
| 9582457 | Camera control interface extension bus | Shoichiro Sengoku, Joseph Cheung | 2017-02-28 |
| 9563398 | Impedance-based flow control for a two-wire interface system with variable frame length | Lalan Jee Mishra, Richard Dominic Wietfeldt, Amit Gil | 2017-02-07 |
| 9553635 | Time based equalization for a C-PHY 3-phase transmitter | Dhaval Sejpal, Chulkyu Lee | 2017-01-24 |
| 9552325 | Camera control interface extension bus | Shoichiro Sengoku, Joseph Cheung | 2017-01-24 |
| 9537687 | Multi-modulation for data-link power reduction and throughput enhancement | Lalan Jee Mishra, Richard Dominic Wietfeldt, James Lionel Panian | 2017-01-03 |
| 9520988 | Adaptation to 3-phase signal swap within a trio | Ohjoon Kwon | 2016-12-13 |
| 9521058 | Multi-wire signaling with matched propagation delay among wire pairs | Shree Krishna Pandey, Arun Chandra Kundu, Chulkyu Lee | 2016-12-13 |
| 9519603 | Method and apparatus to enable multiple masters to operate in a single master bus architecture | Shoichiro Sengoku, Richard Dominic Wietfeldt | 2016-12-13 |
| 9497710 | Multipoint interface shortest pulse width priority resolution | Olaf Hirsch, Richard Dominic Wietfeldt | 2016-11-15 |
| 9455850 | Three phase and polarity encoded serial interface | — | 2016-09-27 |
| 9444612 | Multi-wire single-ended push-pull link with data symbol transition based clocking | Shoichiro Sengoku, Joseph Cheung | 2016-09-13 |
| 9374216 | Multi-wire open-drain link with data symbol transition based clocking | Shoichiro Sengoku, Joseph Cheung | 2016-06-21 |
| 9369237 | Run-length detection and correction | Chulkyu Lee | 2016-06-14 |
| 9363071 | Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches | Shoichiro Sengoku, Chulkyu Lee, Joseph Cheung | 2016-06-07 |
| 9337997 | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state | Shoichiro Sengoku, Chulkyu Lee, Joseph Cheung | 2016-05-10 |