TK

Tsu-Jae King

PT Progressant Technologies: 36 patents #1 of 3Top 35%
SY Synopsys: 17 patents #30 of 2,302Top 2%
University of California: 14 patents #328 of 18,278Top 2%
Xerox: 3 patents #3,111 of 8,622Top 40%
BU Board Of Trustees Leland Stanford Jr University: 1 patents #50 of 153Top 35%
🗺 California: #4,195 of 386,348 inventorsTop 2%
Overall (All Time): #27,987 of 4,157,543Top 1%
72
Patents All Time

Issued Patents All Time

Showing 51–72 of 72 patents

Patent #TitleCo-InventorsDate
6753229 Multiple-thickness gate oxide formed by oxygen implantation Ya-Chin King, Chen Ming Hu 2004-06-22
6754104 Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET 2004-06-22
6727548 Negative differential resistance (NDR) element and memory with reduced soft error rate 2004-04-27
6724655 Memory cell using negative differential resistance field effect transistors 2004-04-20
6700155 Charge trapping device and method for implementing a transistor having a configurable threshold David Liu 2004-03-02
6693027 Method for configuring a device to include a negative differential resistance (NDR) characteristic David Liu 2004-02-17
6686267 Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode 2004-02-03
6686631 Negative differential resistance (NDR) device and method of operating same David Liu 2004-02-03
6680245 Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process David Liu 2004-01-20
6664601 Method of orperating a dual mode FET & logic circuit having negative differential resistance mode 2003-12-16
6596617 CMOS compatible process for making a tunable negative differential resistance (NDR) device David Liu 2003-07-22
6567292 Negative differential resistance (NDR) element and memory with reduced soft error rate 2003-05-20
6518589 Dual mode FET & logic circuit having negative differential resistance mode 2003-02-11
6512274 CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same David Liu 2003-01-28
6479862 Charge trapping device and method for implementing a transistor having a negative differential resistance mode David Liu 2002-11-12
6448622 Polycrystalline silicon-germanium films for micro-electromechanical systems application Andrea Franke, Roger T. Howe 2002-09-10
6413802 Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture Chenming Hu, Vivek Subramanian, Leland Chang, Xuejue Huang, Yang-Kyu Choi +4 more 2002-07-02
6210988 Polycrystalline silicon germanium films for forming micro-electromechanical systems Roger T. Howe, Andrea Franke 2001-04-03
5893949 Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates Jackson Ho 1999-04-13
5707744 Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates Jackson Ho 1998-01-13
5401982 Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions Michael Hack 1995-03-28
5250818 Low temperature germanium-silicon on insulator thin-film transistor Krishna C. Saraswat 1993-10-05