Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including snake open configured fill cells, and the second DOE including stitch open configured fill cells

US Patent 9865583 · Granted Jan 9, 2018

Estimated economic value: $4,527,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems, devices, and methods for performing a non-contact electrical measuremen2025
Systems, devices, and methods for performing a non-contact electrical measuremen2025
Systems, devices, and methods for performing a non-contact electrical measuremen2025
Systems, devices, and methods for performing a non-contact electrical measuremen2025
Systems, devices, and methods for aligning a particle beam and performing a non-2025
Systems, devices, and methods for aligning a particle beam and performing a non-2025
Systems, devices, and methods for aligning a particle beam and performing a non-2025
Embedded system to characterize BTI degradation effects in MOSFETs2025
Embedded system to characterize BTI degradation effects in MOSFETs2025
Embedded system to characterize BTI degradation effects in MOSFETs2025
Systems, devices, and methods for performing a non-contact electrical measuremen2024
Systems, devices, and methods for performing a non-contact electrical measuremen2024