Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Automatic buffer sizing for optimal network-on-chip design

Automatic buffer sizing for optimal network-on-chip design

US Patent 9825887 · Granted Nov 21, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Application mapping on hardened network-on-chip (NoC) of field-programmable gate2025
Flexible on-die fabric interface2024
Flexible on-die fabric interface2023
System on chip (SoC) builder2021
Application mapping on hardened network-on-chip (NoC) of field-programmable gate2021
Repository of integration description of hardware intellectual property for NoC 2021
Interface virtualization and fast path for Network on Chip2020
Interface virtualization and fast path for network on chip2020
Systems and methods for facilitating low power on a network-on-chip2020
Systems and methods for facilitating low power on a network-on-chip2020
Systems and methods for facilitating low power on a network-on-chip2020
Heterogeneous SoC IP core placement in an interconnect to optimize latency and i2020