{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Achieving consistent read times in multi-level non-volatile memory", "item": "https://www.patentleaderboard.com/patent/9811269"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Achieving consistent read times in multi-level non-volatile memory

Achieving consistent read times in multi-level non-volatile memory

US Patent 9811269 · Granted Nov 7, 2017

Estimated economic value: $13,901,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Configuration of a memory device for programming memory cells2025
Managing quality of service by allocating die parallelism with variable queue de2025
Resource management controller2025
Read disturb tracking based on statistical probability2025
Soft read operations with progressive data output2025
Host controlled garbage collection in a solid state drive2025
Flash memory chip that modulates its program step voltage as a function of chip 2025
Simultaneous programming of multiple sub-blocks in NAND memory structures2025
Method and apparatus for improving write uniformity in a memory device2025
Cache processes with adaptive dynamic start voltage calculation for memory devic2025
NAND-based storage device with partitioned nonvolatile write buffer2025
Variable error correction codeword packing to support bit error rate targets2024