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Home › Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells

Process for making and using a semiconductor wafer containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including via open configured fill cells, and the second DOE including stitch open configured fill cells

US Patent 9786649 · Granted Oct 10, 2017

Estimated economic value: $1,101,000 ⓘ

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