Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Chip package method for reducing chip leakage current

Chip package method for reducing chip leakage current

US Patent 9786521 · Granted Oct 10, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Stacked package structure and stacked packaging method for chip2025
Method of manufacturing chip packaging structure with dissipation layer, flange 2023
Stacked package structure and stacked packaging method for chip2022
Chip packaging structure with heat dissipation layer, flange and sealing pin2022
Stacked package structure and stacked packaging method for chip2020
Integrated package assembly for switching regulator2020
Package structure and method thereof2020
Package structure and method therof2019
Package assembly having interconnect for stacked electronic devices and method f2018
Integrated package assembly for switching regulator2018
Chip package structure and manufacturing method therefor2017
Flip chip package structure and fabrication process thereof2017