Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules

Method for incorporating stress sensitive chip scale components into reconstructed wafer based modules

US Patent 9735128 · Granted Aug 15, 2017

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods and devices for improved space utilization in wafer based modules2020
Method and apparatus for forming multi-layered vias in sequentially fabricated c2019
Method and apparatus for using universal cavity wafer in wafer level packaging2019
Reconstructed wafer based devices with embedded environmental sensors and proces2019
Closely spaced array of penetrating electrodes2019
Devices and methods for detecting counterfeit semiconductor devices2018
Method and apparatus for using universal cavity wafer in wafer level packaging2017
Method for interconnecting die and substrate in an electronic package2016
Method for embedding a chipset having an intermediary interposer in high density2016
Three dimensional microelectronic components and fabrication methods for same2014
Interconnection of through-wafer vias using bridge structures2009
Method of producing a MEMS device2008