{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Via and chamfer control for advanced interconnects", "item": "https://www.patentleaderboard.com/patent/9691659"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Via and chamfer control for advanced interconnects

Via and chamfer control for advanced interconnects

US Patent 9691659 · Granted Jun 27, 2017

Estimated economic value: $2,603,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Local interconnects having different material compositions2025
Layered bottom electrode dielectric for embedded MRAM2025
Recessed local interconnect semiconductor memory device2025
MRAM structure with a T-shaped ferromagnetic layer2025
Back-end-of-line thin film resistor2025
MRAM bottom electrode contact with taper profile2025
Top via interconnect with airgap2025
MRAM device with octagon profile2025
Dual-damascene fav interconnects with dielectric plug2025
Top via containing random-access memory cross-bar array2025
Magneto-resistive random access memory with hemispherical top electrode2025
Magnetoresistive random-access memory (MRAM) with preserved underlying dielectri2025