Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Fail-safe I/O to achieve ultra low system power

Fail-safe I/O to achieve ultra low system power

US Patent 9627035 · Granted Apr 18, 2017

Estimated economic value: $15,979,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power-on-reset signal isolation during lower power mode2025
Process for polymerizing fluoromonomers using a combination of fluorinated and n2025
Process for preparing fluoropolymers and fluoroelastomers in presence of a non f2025
Floating pin detection2025
Ultra-low power, high speed poly fuse eprom2025
System on a chip with an integrated configurable safety master microcontroller u2025
Low noise high precision voltage reference2024
Temperature drift correction in a voltage reference2024
Accessing error statistics from DRAM memories having integrated error correction2024
Trim/test interface for devices with low pin count or analog or no-connect pins2024
Integrated circuit with low power mode management2024
Accuracy trim architecture for high precision voltage reference2024