Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Trim/test interface for devices with low pin count or analog or no-connect pins

Trim/test interface for devices with low pin count or analog or no-connect pins

US Patent 12131799 · Granted Oct 29, 2024

Estimated economic value: $41,373,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Process for polymerizing fluoromonomers using a combination of fluorinated and n2025
Process for preparing fluoropolymers and fluoroelastomers in presence of a non f2025
Floating pin detection2025
Floating pin detection2025
Ultra-low power, high speed poly fuse eprom2025
Low noise high precision voltage reference2024
Low noise high precision voltage reference2024
Temperature drift correction in a voltage reference2024
Accuracy trim architecture for high precision voltage reference2024
Fail-safe switch for multidomain systems2024
Voltage monitor using a capacitive digital-to-analog converter2023
Supply voltage regulator2023