Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking

Offset insensitive quadrature clock error correction and duty cycle calibration for high-speed clocking

US Patent 9602082 · Granted Mar 21, 2017

Estimated economic value: $15,156,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Methods and apparatuses for wavelength locking for optical wavelength division m2025
Methods and apparatuses for maximizing output modulation amplitude for optical w2025
Circuits and methods for wavelength locking of optical receiver WDM filters2024
Frequency detector for clock data recovery2024
Heterogeneous integration module comprising thermal management apparatus2023
Frequency detector for clock data recovery2022
Integrated electrical/optical interface with two-tiered packaging2021
Inductor design in active 3D stacking technology2021
Method and system for correlation of a behavioral model to a circuit realization2021
Temperature-locked loop for optical elements having a temperature-dependent resp2021
Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) c2020
Apparatus and method to reduce lock time via frequency band calibration2020