Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Systems, methods and devices for programming a multilevel resistive memory cell

Systems, methods and devices for programming a multilevel resistive memory cell

US Patent 9530497 · Granted Dec 27, 2016

Estimated economic value: $13,056,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Decoding architecture for memory devices2025
Memory cell formation in three dimensional memory arrays using atomic layer depo2025
Accessing memory cells in a vertical memory array2025
Memory devices having one-time-programmable fuses and/or antifuses formed from t2025
Pillar and word line plate architecture for a memory array2025
Word line structures for three-dimensional memory arrays2025
Sparse piers for three-dimensional memory arrays2025
Dense piers for three-dimensional memory arrays2025
Decoder architectures for three-dimensional memory devices2025
Memory cells with sidewall and bulk regions in vertical structures2025
Memory device and method for manufacturing the same2025
Split pillar architectures for memory devices2024