Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Programmable power reduction technique using transistor threshold drops

Programmable power reduction technique using transistor threshold drops

US Patent 9496871 · Granted Nov 15, 2016

Estimated economic value: $14,364,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Tiled compute and programmable logic array2025
Methods to extend NoC interconnect across multiple dice in 3D2025
Redundancy scheme for activating circuitry on a base die of a 3D stacked device2025
Adaptive integrated programmable device platform2025
Adding soft logic to flush a pipeline and reduce current ramp2025
Yield recovery scheme for memory2024
System and method for secure deconstruction sensor in a heterogeneous integratio2024
Forming and/or configuring stacked dies2024
Universal interposer for a semiconductor package2024
Clock tree routing in a chip stack2024
Compute dataflow architecture2023
Adaptive integrated programmable device platform2023