Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multi-level clock signal distribution network and integrated circuit

Multi-level clock signal distribution network and integrated circuit

US Patent 9459651 · Granted Oct 4, 2016

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Hybrid FIFO buffer2021
Systems and methods for transferring data with a dual-line first-in-first-out (F2020
Method and apparatus for transmitting signals over long distances on an integrat2020
Method and control device for recovering NBTI/PBTI related parameter degradation2016
Method and apparatus for generating gate-level activity data for use in clock ga2015
Method for power reduction and a device having power reduction capabilities2013
Device and method for testing a device2012
Device and method for testing a circuit2012
Integrated circuit and a method for recovering from a low-power period2010
Non-high impedence device and method for reducing energy consumption2009
Apparatus and method for implementing a linearly approximated log map algorithm2004