{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Defect reduction with rotated double aspect ratio trapping", "item": "https://www.patentleaderboard.com/patent/9443940"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Defect reduction with rotated double aspect ratio trapping

Defect reduction with rotated double aspect ratio trapping

US Patent 9443940 · Granted Sep 13, 2016

Estimated economic value: $3,651,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Electronically programmable fuse with heating transistors2025
Lateral phototransistor2025
Semiconductor-on-insulator field-effect transistors including stress-inducing co2025
Vertically stacked cascode bipolar junction transistor (BJT) pair sensor2025
Stacked complementary field effect transistors2025
Power distribution network with backside power rail2025
Tunnel field effect transistor devices2025
Forksheet transistor with dual depth late cell boundary cut2025
Hybrid stacked field effect transistors2025
Gate induced drain leakage reduction in FinFETs2025
Textured cobalt aluminum/magnesium-aluminum-oxide pedestal for memory devices2025
Semiconductor device with void under source/drain region for backside contact2025