Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low density parity check circuit

Low density parity check circuit

US Patent 9411684 · Granted Aug 9, 2016

Estimated economic value: $9,565,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Temporary parity buffer allocation for zones in a parity group2025
Peak power management priority override2025
Configurable buffered I/O for memory systems2025
Serial interface for an active input/output expander of a memory sub-system2024
Ball grid array storage for a memory sub-system2024
Management of erase suspend and resume operations in memory devices2024
Active input/output expander of a memory sub-system2023
Handling of host-initiated requests in memory sub-systems2023
Managing sequential write performance consistency for memory devices2022
Apparatus having a multiplexer for passive input/output expansion2022
Selection component that is configured based on an architecture associated with 2022
Ball grid array storage for a memory sub-system2022