Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabrication transistor with non-uniform stress layer with stress concentrated regions

Method of fabrication transistor with non-uniform stress layer with stress concentrated regions

US Patent 9343573 · Granted May 17, 2016

Estimated economic value: $201,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Layout structure forming method of sense amplifier and layout structure of sense2025
Photoresist and method2025
In-situ deposition and densification treatment for metal-comprising resist layer2025
Photoresist layer surface treatment, cap layer, and method of forming photoresis2025
Method of forming conductive layer of semiconductor device2025
Method for forming and using mask2025
Semiconductor device and method2025
Method for forming interconnect structure2025
Semiconductor device and method for fabricating the same2025
Method for fabricating semiconductor device2025
Method for forming semiconductor device2025
Humanized anti-human neurotensin receptor 1 antibodies and their uses2024