Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure

Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) having a ferroelectric capacitor aligned with a three dimensional transistor structure

US Patent 9318693 · Granted Apr 19, 2016

Estimated economic value: $2,645,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Aggregation of global story based on analyzed data2025
Non-invasive radio frequency sensor2025
Wearable health interface for controlling internet of things devices2025
Live event recording method and system2025
RF material detection device with smart scanning multiple axis gimbal integrated2025
RF-based special material detection system with secure multi-dimensional authent2025
Method for replaying a bet and sharing2025
Interferon regulatory factor 5 inhibitors and uses thereof2025
Method of using telemetry data to determine wager odds at a live event2025
Method of rewarding non-dangerous behavior2025
Business variable optimization for manufacture or supply of designed products2025
Intelligent hybrid power system for electrical vehicles2025