Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Techniques for detection and treating memory hole to local interconnect marginality defects

Techniques for detection and treating memory hole to local interconnect marginality defects

US Patent 9224502 · Granted Dec 29, 2015

Estimated economic value: $9,346,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Non-volatile memory with efficient testing2025
Clamped semiconductor wafers and semiconductor devices2025
Non-volatile memory with efficient testing during erase2023
System and method for warpage detection in a CMOS bonded array2023
Non-volatile memory with efficient testing during erase2023
Prevention of latent block fails in three-dimensional NAND2023
Memory controller for resolving string to string shorts2023
Semiconductor device including coupled bond pads having differing numbers of pad2022
Straight wirebonding of silicon dies2022
System and method for die crack detection in a CMOS bonded array2022
Memory controller for resolving string to string shorts2022
Semiconductor device including vertical bond pads2022