Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Parallel processing for low latency network address translation

Parallel processing for low latency network address translation

US Patent 9154415 · Granted Oct 6, 2015

Estimated economic value: $17,408,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Programmable traffic ingress direction for reduced latency in a DPU2025
Application-aware links2025
Designated forwarder selection for multihomed hosts in an ethernet virtual priva2025
Designated forwarder selection for multihomed hosts in an ethernet virtual priva2025
Exporting real time network traffic latency and buffer occupancy2025
System and method to measure and score application health via correctable errors2024
System and method to measure and score application health via correctable errors2024
Designated forwarder selection for multihomed hosts in an ethernet virtual priva2024
Designated forwarder selection for multihomed hosts in an ethernet virtual priva2024
Application-aware links2024
Timestamping packets in a network2024
Fast forwarding re-convergence of switch fabric multi-destination packets trigge2023