Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multi-port SRAM with shared write bit-line architecture and selective read path for low power operation

Multi-port SRAM with shared write bit-line architecture and selective read path for low power operation

US Patent 9142285 · Granted Sep 22, 2015

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Adaptive control circuit of static random access memory2024
Data storage apparatus and data prediction method thereof2022
Neural-signal amplifier and multi-channel neural-signal amplifying system2022
Data storage system, data storage device and management method thereof2021
Disk managing method and raid controller2019
Port multiplier system and operation method2019
Pre-processing circuit with data-line DC immune clamping and associated method a2019
Memory circuit and layout structure of a memory circuit2017
Ten-transistor dual-port SRAM with shared bit-line architecture2014
Ten-transistor dual-port SRAM with shared bit-line architecture2014
Static random access memory apparatus and bit-line voltage controller thereof2014
Oscillato based on a 6T SRAM for measuring the bias temperature instability2014