Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Writeback mechanisms for improving far memory utilization in multi-level memory architectures

Writeback mechanisms for improving far memory utilization in multi-level memory architectures

US Patent 9032099 · Granted May 12, 2015

Estimated economic value: $21,151,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Load store bank aware thread scheduling techniques2025
Multi-render partitioning2025
Graphics processing unit processing and caching improvements2025
Immediate offset of load store and atomic instructions2025
Coordination and increased utilization of graphics processors during inference2025
Regional adjustment of render rate2025
Sharing register file usage between fused processing resources2025
Sharing register file usage between fused processing resources2025
Multicore processor with each core having independent floating point datapath an2025
Neural network optimization mechanism2025
Utilizing structured sparsity in systolic arrays2025
System, apparatus and method for increasing performance in a processor during a 2025