Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands

Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands

US Patent 9009450 · Granted Apr 14, 2015

Estimated economic value: $12,929,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Modular open system architecture for common intelligence picture generation2025
Register addressing information for data transfer instruction2025
Processing instructions selected from a first instruction set in a first process2025
Apparatus and method for performing a splice of vectors based on location and le2024
Testing bit values inside vector elements2022
Data processing2022
Element by vector operations in a data processing apparatus2022
Vector length querying instruction2022
Data structure relinquishing2022
Vector add-with-carry instruction2021
Vector interleaving in a data processing apparatus2021
Data processing2021