Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods for layout verification for polysilicon cell edge structures in FinFET standard cells

Methods for layout verification for polysilicon cell edge structures in FinFET standard cells

US Patent 8943455 · Granted Jan 27, 2015

Estimated economic value: $4,163,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Gamepad2025
Projection system and calibration method thereof2024
Light source module2024
Dual handle speed adjustment device and lawn mower using same2023
Light source module and projection device2023
Package structure and method for forming the same2022
Layout checking system and method2021
Method for forming patterns2021
Testing system and testing method2020
Projection system and optimizing method thereof2020
Layout checking system and method2020
Semiconductor structure and method for operating the same2018