{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Managing misaligned DMA addresses", "item": "https://www.patentleaderboard.com/patent/8918552"}]}
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Managing misaligned DMA addresses

US Patent 8918552 · Granted Dec 23, 2014

Estimated economic value: $3,729,000 ⓘ

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