Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Providing a feedback loop in a low latency serial interconnect architecture

Providing a feedback loop in a low latency serial interconnect architecture

US Patent 8711018 · Granted Apr 29, 2014

Estimated economic value: $15,282,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System, method and apparatus for link training during a clock switch event2025
Component firmware interaction using hardware registers2025
Provisioning a reference voltage based on an evaluation of a pseudo-precision re2024
Component firmware interaction using hardware registers2023
Technologies for timestamping with error correction2023
Technologies for timestamping with error correction2023
Techniques for link partner error reporting2021
Technologies for timestamping with error correction2021
PLL capacitor swap technique and low jitter dynamic Digital Controlled Oscillato2021
Techniques for link partner error reporting2021
High-speed, low power, low kickback noise comparator suitable for a multi-compar2020
Low latency re-timer2020