Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Controlling select gate voltage during erase to improve endurance in non volatile memory

Controlling select gate voltage during erase to improve endurance in non volatile memory

US Patent 8542535 · Granted Sep 24, 2013

Estimated economic value: $13,692,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Dual-way sensing scheme for better neighboring word-line interference2025
Open block read ICC reduction2025
Dynamic 1-tier scan for high performance 3D NAND2025
High performance verify techniques in a memory device2025
Non-volatile memory with erase depth detection and adaptive adjustment to progra2025
Apparatus and method for detecting neighbor plane erase failures2025
Data retention-specific refresh read2025
Three-bit-per-cell programming using a four-bit-per-cell programming algorithm2025
CELSRC voltage separation between SLC and XLC for SLC program average ICC reduct2025
Low power read method and a memory device capable thereof2025
Pump skip for fast single-level cell non-volatile memory2025
High speed multi-level cell (MLC) programming in non-volatile memory structures2024