Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network

US Patent 8525569 · Granted Sep 3, 2013

Estimated economic value: $4,698,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Providing deterministic frequency and voltage enhancements for a processor2025
Dynamic guard band with timing protection and with performance protection2024
Dynamic guard band with timing protection and with performance protection2024
Proactive voltage droop reduction and/or mitigation in a processor core2023
On-chip supply noise voltage reduction or mitigation using local detection loops2023
Proactive voltage droop reduction and/or mitigation in a processor core2022
On-chip supply noise voltage reduction or mitigation using local detection loops2021
Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage2021
Determining clock signal quality using a plurality of sensors2020
Determining clock signal quality using a plurality of sensors2020
Proactive voltage droop reduction and/or mitigation in a processor core2020
Non-volatile memory with reduced program speed variation2019