Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Measurement of partially depleted silicon-on-insulator CMOS circuit leakage current under different steady state switching conditions

Measurement of partially depleted silicon-on-insulator CMOS circuit leakage current under different steady state switching conditions

US Patent 8310269 · Granted Nov 13, 2012

Estimated economic value: $6,514,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Circuits for converting SFQ-based RZ and NRZ signaling to bilevel voltage NRZ si2023
Trilayer Josephson junction structure with small air bridge and no interlevel di2021
Trilayer Josephson junction structure with small air bridge and no interlevel di2019
Trilayer Josephson junction structure with small air bridge and no interlevel di2019
Single-flux-quantum probabilistic digitizer2017
Single-flux-quantum probabilistic digitizer2017
Trilayer josephson junction structure with small air bridge and no interlevel di2017
Modular array of fixed-coupling quantum systems for quantum information processi2016
Single level of metal test structure for differential timing and variability mea2015
Single level of metal test structure for differential timing and variability mea2015
Reducing performance degradation in backup semiconductor chips2015
Single level of metal test structure for differential timing and variability mea2015