Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof

Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof

US Patent 8310040 · Granted Nov 13, 2012

Estimated economic value: $13,396,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Power distribution circuits for electrically powered aircraft2025
Electronic connection assembly2025
Power overlay module with thermal storage2025
Semiconductor device package and method of forming2024
Ultra-thin embedded semiconductor device package and method of manufacturing the2023
Ultra-thin embedded semiconductor device package and method of manufacturing the2023
Power overlay module and method of assembling2023
Power electronics package and method of manufacturing thereof2021
Power electronics package and method of manufacturing thereof2021
Electronics package having a multi-thickness conductor layer and method of manuf2020
Stacked electronics package and method of manufacturing thereof2020
Interconnect devices for electronic packaging assemblies2020