Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks

Area-efficient memory built-in-self-test circuitry with advanced debug capabilities for distributed memory blocks

US Patent 8259522 · Granted Sep 4, 2012

Estimated economic value: $28,718,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Corporate board management system2016
Method and apparatus for die testing2015
Integrated circuit with configurable test pins2012
Area-efficient memory built-in-self-test circuitry with advanced debug capabilit2011
Area-efficient memory built-in-self-test circuitry with advanced debug capabilit2011
Method and apparatus for routing efficient built-in self test for on-chip circui2010
Pipelined scan structures for testing embedded cores2009
Testing hard-wired IP interface signals using a soft scan chain2008
Automatic test configuration generation facilitating repair of programmable circ2008
Constraint-driven test generation for programmable logic device integrated circu2008
Soft error tolerance for configuration memory in programmable devices2008
Apparatus and method for encrypting security sensitive data2007