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Home › Modeling and simulating device mismatch for designing integrated circuits

Modeling and simulating device mismatch for designing integrated circuits

US Patent 8176463 · Granted May 8, 2012

Estimated economic value: $16,578,000 ⓘ

Assignee

Cadence Design Systems

Inventors

Donald J. O'Riordan (44 patents)
Arthur Schaldenbrand (1 patents)
John P. O'Donovan (25 patents)

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