Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection

Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection

US Patent 8143672 · Granted Mar 27, 2012

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Stacked memory device, optical proximity correction (OPC) verifying method, meth2019
Method and system for verifying layout of integrated circuit including vertical 2018
Bit line sense amplifier layout array, layout method, and apparatus having the s2013
Area-efficient data line layouts to suppress the degradation of electrical chara2013
Sub-word line driver circuit and semiconductor memory device having the same2012
Bit line sense amplifier of semiconductor memory device having open bit line str2011
Semiconductor device having stacked decoupling capacitors2011
Stacked memory cell for use in high-density CMOS SRAM2011
Bit line sense amplifier of semiconductor memory device having open bit line str2011
Semiconductor memory device and layout method thereof2010
Layout structure of sub-world line driver and forming method thereof2010
Bit line sense amplifier of semiconductor memory device having open bit line str2009