{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Apparatus for implementing processor bus speculative data completion", "item": "https://www.patentleaderboard.com/patent/8103930"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus for implementing processor bus speculative data completion

Apparatus for implementing processor bus speculative data completion

US Patent 8103930 · Granted Jan 24, 2012

Estimated economic value: $7,514,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Asynchronous completion notification in a multi-core data processing system2024
Efficient selection of a particular processor thread for handling an interrupt2023
Write disturb refresh rate reduction using write history buffer2022
Configurable write command delay in nonvolatile memory2021
Managing efficient selection of a particular processor thread for handling an in2021
Preventing hazard flushes in an instruction sequencing unit of a multi-slice pro2020
Operation of a multi-slice processor with an expanded merge fetching queue2020
Techniques for issuing interrupts in a data processing system with multiple scop2020
Techniques for issuing interrupts in a data processing system with multiple scop2020
Supporting access control list rules that apply to TCP segments belonging to ‘es2020
Managing efficient selection of a particular processor thread for handling an in2019
Operation of a multi-slice processor with dynamic canceling of partial loads2019