Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Miss-under-miss processing and cache flushing

Miss-under-miss processing and cache flushing

US Patent 8037281 · Granted Oct 11, 2011

Estimated economic value: $4,727,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Structural rod2022
Offloaded disaggregated storage architecture2020
Non-volatile memory over fabric controller with memory bypass2020
Redundancy coding stripe based on coordinated internal address scheme across mul2019
Streaming translation lookaside buffer2019
Silent active page migration faults2019
Fully virtualized TLBs2019
Sharing translation lookaside buffer resources for different traffic classes2018
Process and apparatus to reduce declared capacity of a storage device by making 2017
Process and apparatus to reduce declared capacity of a storage device by reducin2017
Triggering a process to reduce declared capacity of a storage device in a multi-2017
Process and apparatus to reduce declared capacity of a storage device by moving 2017