Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method and context switch device for implementing design-for-testability functionality of latch-based register files

Method and context switch device for implementing design-for-testability functionality of latch-based register files

US Patent 7979684 · Granted Jul 12, 2011

Estimated economic value: $19,878,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Multi-port memory circuits2016
Dual-voltage domain memory buffers, and related systems and methods2015
Sense amplifier including a level shifter2015
Unified virtual addressed register file2014
Voltage level shifter with dynamic circuit structure having discharge delay trac2014
Efficient transformation techniques for video coding2014
Architecture and method for eliminating store buffers in a DSP/processor with mu2013
Architecture and method for eliminating store buffers in a DSP/processor with mu2013
Multi-voltage level, multi-dynamic circuit structure device2013
Cached memory system and cache controller for embedded digital signal processor2012
Tiled cache for multiple software programs2011
Circuits and methods for sleep state leakage current reduction2011