Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Methods for fabricating a stressed MOS device

Methods for fabricating a stressed MOS device

US Patent 7902008 · Granted Mar 8, 2011

Estimated economic value: $12,082,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

High resistivity silicon-on-insulator substrate comprising an isolation region2025
High resistivity semiconductor-on-insulator wafer and a method of manufacture2023
High resistivity single crystal silicon ingot and wafer having improved mechanic2023
High resistivity single crystal silicon ingot and wafer having improved mechanic2023
High resistivity SOI wafers and a method of manufacturing thereof2023
Method of preparing an isolation region in a high resistivity silicon-on-insulat2023
Electromagnetic casting systems including furnaces and molds for producing silic2022
Semiconductor on insulator structure comprising a buried high resistivity layer2022
Method of preparing an isolation region in a high resistivity silicon-on-insulat2022
High resistivity single crystal silicon ingot and wafer having improved mechanic2021
High resistivity semiconductor-on-insulator wafer and a method of manufacturing2021
High resistivity SOI wafers and a method of manufacturing thereof2021